Neuromorphic engineers are studying the nervous system and trying to emulate its function and organization in their computational and robotics systems. They are hoping to match (or perhaps even exceed) the human brain in vision, hearing, pattern recognition and learning tasks (Boahen 2005). By following this design philosophy, they have been able to create practical devices that operate in real time and consume less power than standard digital designs (Douglas 2005). One of the earliest neuromorphic devices was the silicon neuron which was able to mimic the ion currents that cause nerve impulses in biological neurons (Mahowald 1991). Others quickly followed focusing on emulating the eye (retina) and ear (cochlea) (Etienne-Cummings 1996, Andreou 1995, Mead 1988, Lyon 1988, Mahowald 1991b, Boahen 1992, Watts 1992, Koch 1996, Sarpeshkar 1996, van Schaik 1996, and many others).
More recently, neuromorphic engineers have been able to create more complex circuits that are better at emulating human senses capturing more of the dynamics and behaviors of their biological counterparts (Culurciello 2006, Zaghloul 2006, Hamilton 2008, Wen 2009) as a result of advances in integrated circuit technologies. As silicon engineering technology continues to improve, they move beyond sensory modalities to implementing various cortical areas.
There are over a hundred billion neurons and over a hundred trillion interconnections between them in the human brain. Designing parts of the cortex therefore requires a network of millions of neurons with billions of connections. This means that the silicon neuron must be compact (small area) and efficient (low power) so that as many of them as possible can be put on a single silicon chip. They must also be robust, able to generate most of the spiking and bursting patterns of biological neurons.
On the one hand, there are the simple models which are basic integrate-and-fire neurons. They integrate synaptic inputs onto the membrane capacitor and generate action potentials when the membrane voltage exceeds a preset threshold. At the other extreme are the Hodgkin-Huxley type models which capture the details of ion currents and conductances in the neuron. A tradeoff exists between the neuron complexity and the behavior of the model. A detailed neuron description is usually large and inefficient which allows for the implementation of only a simple network while a simple neuron description is usually not robust enough to emulate the dynamics of biological neurons.
The Izhikevich (Izhikevich 2003), Mihalas-Niebur (Mihalas 2009) and similar models lie between these extremes. They are curve-fitting models capable of producing the twenty known features of biological neurons. The configuration parameters of the Mihalas-Niebur model have biophysical meanings. In addition, its equations are also completely linear making it very efficient in its implementation. An array of M-N neurons (IFAT 3G) has been implemented in a 3D CMOS process to capture the 3D interconnections, parallel processing and computation observed in biological neurons (Folowosele 2009). The silicon neurons were placed on one layer, synapses and interconnections on the second layer and the communications circuitry on the third layer (Figure 1).
Other large arrays of neurons have been designed to emulate networks of biological neurons (Goldberg 2001, Indiveri 2004, Zou 2006, Ros 2006, Arthur 2006, Taba 2006, Horiuchi 2001, Paz 2005, Choi 2005, Serrano-Gotarredona 2006). Many of these arrays are specific to neural processes such as spatial frequency and orientation (Choi 2005), acoustic localization (Horiuchi 2001) and retinotopic maps (Taba 2006), while others can be adapted to multiple tasks (Goldberg 2001, Vogelstein 2007a, Indiveri 2004, Paz 2005).
More recently, large systems are being put together which consists of multiple chips. The CAVIAR system consists of four chips, each containing an array of neurons. The largest system of neuromorphic chips working together to solve a common problem, CAVIAR has about 45,000 neurons and 5 million synapses (see http://www.ini.uzh.ch/~tobi/caviar/). The wafer-scale array of silicon neurons by the FACETS consortium (schemmel2008a) consists of chips with 512 neurons and 256 synapses. When finished, it is expected to have over 200,000 neurons on it (see https://facets.kip.uni-heidelberg.de/index.html). Before this happens however, the system efficiency, power consumption, and fabrication yield must be improved. Neurogrid designed by The Brains in Silicon group at Stanford University consists of 16 VLSI chips which simulate over a million neurons in real time while consuming a power of only 1W. Neurogrid requires many parameters and is sensitive to variations in the fabrication process. Nonetheless, it is a remarkable feat given the large number of analog neuromorphic neurons which are connected via a state of the art asynchronous communications protocol (see http://www.stanford.edu/group/brainsinsilicon/).
The 4th generation Johns Hopkins University system (IFAT 4G) will consist of over 60,000 neurons (10 chips) with 120 million fully programmable synaptic connections. Unlike the other systems, it is able to achieve unlimited connectivity and reprogrammability by not having hardwired connections between neurons. Instead network topologies and synaptic parameters are stored in a RAM lookup table that is accessed by a field programmable gate array (FPGA) which routes spikes between the neurons. The individual neuron chips have been implemented on a 9 mm2 chip in an old technology (0.5um CMOS). Clearly, the over 6K neurons per chip can be easily increased by a factor of ~100 by using a larger chip area and a state of the art process. Two neuron models can be implemented – a leaky integrate-and-fire model or an adaptive threshold model based on the Mihalas-Niebur neuron model. To date (2010), an earlier version of the IFAT (IFAT 2G) with approximately 10,000 neurons (with little mismatch) has been used to implement a small example of the HMAX visual cortex model for spike-based object recognition (see http://etienne.ece.jhu.edu/ projects /ifat/index.html). With the increased size, the communications between the neurons will have to be locally parallelized in order to increase network capacity. The need for the routing FPGA (distributed to improve routing bandwidth) will also limit how low the power can be reduced.
These neural arrays and neuromorphic systems will serve as a platform for testing various theories of the functions, computations and organization in parts of the nervous system. Thus providing a better understanding of the biology and aiding in the development of neural prostheses. In addition, more robots can be designed with parts that emulate the nervous system leading to more intelligent robots that are able to interact with their environment with only limited human involvement.
- A. Andreou, R. Meitzler, K. Strohbehn, and K. Boahen, “Analog VLSI neuromorphic image acquisition and pre-processing systems,” Neural Networks, vol. 8, no. 7-8, pp. 1323–1347, 1995.
- J V Arthur and K Boahen, “Learning in Silicon: Timing is Everything,” Advances in Neural Information Processing Systems 18, B Sholkopf and Y Weiss, Eds, pp 75-82, MIT Press, 2006.
- K. Boahen and A. Andreou, “A contrast sensitive silicon retina with reciprocal synapses,” Advances in Neural Information Processing Systems, vol. 4, pp. 764–772, 1992.
- K. Boahen, “Neuromorphic microchips.” Scientific American, vol. 292, no. 5, pp. 56–63, 2005
- T.Y.U. Choi, P.A. Merolla, J.V. Arthur, K.A. Boahen, and B.E. Shi, “Neuromorphic implementation of orientation hypercolumns,” IEEE Transactions on Circuits and Systems, vol. 52, no. 6, June 2005.
- E. Culurciello, R. Etienne-Cummings, and K. Boahen, “A biomorphic digital image sensor,” IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 281–294, 2003.
- R. Douglas, M. Mahowald, and C. Mead, “Neuromorphic analogue VLSI,” Annual review of neuroscience, vol. 18, no. 1, pp. 255–281, 1995.
- R. Etienne-Cummings and J. Van der Spiegel, “Neuromorphic vision sensors,” Sensors & Actuators: A. Physical, vol. 56, no. 1-2, pp. 19–29, 1996.
- F. Folowosele, R.J. Vogelstein, and R. Etienne-Cummings, “Real-Time Silicon Implementation of V1 in Hierarchical Visual Informaiton Processing,” Proceedings of the IEEE Biomedical Circuits and Systems Conference (BioCAS), Baltimore, Maryland, Nov. 2008
- F. Folowosele, T.J. Hamilton, A. Harrison, A. Cassidy, A.G. Andreou, S. Mihalas, E. Niebur, and R. Etienne-Cummings, “A Switched Capacitor Implementation of the Generalized Linear Integrate-and-Fire Neuron,” IEEE ISCAS 2009, May 2009.
- D.H. Goldberg, G. Cauwenberghs, and A.G. Andreou, “Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons,” Neural Networks, vol. 14, pp. 781-793, 2001.
- T. Hamilton, J. Tapson, C. Jin, and A. van Schaik, “Analogue VLSI implementations of two dimensional, nonlinear, active cochlea models,” in IEEE Biomedical Circuits and Systems Conference, 2008. BioCAS 2008, 2008, pp. 153–156.
- T. Horiuchi and K. Hynna, “Spike-based VLSI modeling of the ILD system in the echolocating bat,” Neural Netw., vol. 14, pp. 755–762, 2001.
- G. Indiveri, E. Chicca, and R.J. Douglas, “A VLSI reconfigurable network of integrate-and-fire neurons with spike-based learning synapses,” Euro. Symp. on Artificial Neural Networks, pp. 405-410, 2004.
- E. Izhikevich, N. Desai, E. Walcott, and F. Hoppensteadt, “Bursts as a unit of neural information: selective communication via resonance* 1,” Trends in Neurosciences, vol. 26, no. 3, pp. 161–167, 2003.
- C. Koch and B. Mathur, “Neuromorphic vision chips,” IEEE Spectrum, vol. 33, no. 5, pp. 38–46, 1996.
- R. Lyon and C. Mead, “An analog electronic cochlea,” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 36, no. 7, pp. 1119–1134, 1988.
- M. Mahowald and R. Douglas, “A silicon neuron.” Nature, vol. 354, no. 6354, p. 515, 1991.
- M. Mahowald, “Silicon retina with adaptive photoreceptors,” Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series, vol. 1473, pp. 52–58, 1991b.
- C. Mead and M. Mahowald, “A silicon model of early visual processing,” Neural Networks, vol. 1, no. 1, pp. 91–97, 1988.
- S. Mihalas and E. Niebur, “A generalized linear integrate-and-fire neural model produces diverse spiking behaviors,” Neural Computation, vol. 21, no. 3, pp. 704–718, 2009.
- R. Paz, F. Gomez-Rodriguez, M. Rodriguez, A. Linares-Barranco, G. Jimenez, and A. Civit, “Test infrastructure for address-event-representation communications,” in Lecture Notes in Computer Science. Berlin, Germany: Springer-Verlag, vol. 3512, pp. 518–526, 2005.
- M. Riesenhuber and T. Poggio, “Hierarchical models of object recognition in cortex,” Nature Neuroscience, vol. 2, no. 11, p. 1019, 1999.
- E. Ros, E.M. Ortigosa, R. Agis, R. Carrillo, and M. Arnold, “Real-time computing platform for spiking neurons (RT-spike),” IEEE Trans. Neural Netw., vol. 17, no. 4, pp. 1050-1063, Jul. 2006.
- R. Sarpeshkar, R. Lyon, and C. Mead, “An analog VLSI cochlea with new transconductance amplifiers andnonlinear gain control,” in 1996 IEEE International Symposium on Circuits and Systems, 1996. ISCAS’96.,’Connecting the World’., vol. 3, 1996.
- J. Schemmel, J. Fieres and K. Meier, “Wafer-scale integration of analog neural networks,” IEEE International Joint Conference on Neural Networks (IJCNN), pp. 431-438, 2008a.
- J. Schemmel, J. Fieres and K. Meier, “Realizing biological spiking network models in a configurable wafer-scale hardware system,” IEEE International Joint Conference on Neural Networks (IJCNN), pp. 969-976, 2008b.
- R. Serrano-Gotarredona, M. Oster, P. Lichsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gomez-Rodriguez, L. Camunas-Mesa, R. Berner, M. Rivas-Perez, T. Delbruck, S-C, Liu, R. Douglas, P. Hafliger, G. Jimenez-Moreno, A.C. Ballcels, T. Serrano-Gotarredona, A.J. Acosta-Jimenez and B. Linares-Barranco, “CAVIAR: A 45k neuron, 5m synapse, 12 G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking,” IEEE Transactions on Neural Networks, vol. 20, no. 9, 2009
- R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. L.-B. and R. Paz-Vicente, F. Gomez-Rodrıguez, H. K. Riis, T.Delbruck, S.-C. Liu, S. Zahnd, A. M. Whatley, R.Douglas, P. Hafliger, G. Jimenez-Moreno, A. Civit, T.Serrano-Gotarredona, A. Acosta-Jim´enez, and B. Linares-Barranco, “AER building blocks for multilayer multi-chip neuromorphic vision systems,” in Advances in Neural Information Processing Systems 18, Y.Weiss, B. Sch¨olkopf, and J. Platt, Eds. Cambridge, MA: MIT Press, 2006, pp. 1217–1224.
- B Taba and K Boahen, “Silicon Growth Cones Map Silicon Retina,” Advances in Neural Information Processing Systems 18, B Sholkopf and Y Weiss, Eds, pp 1329-1336, MIT Press, 2006.
- A. van Schaik, E. Fragni`ere, and E. Vittoz, “Improved silicon cochlea using compatible lateral bipolar transistors,” Advances in Neural Information Processing Systems, pp. 671–677, 1996.
- R.J. Vogelstein, U. Mallik, J.T. Vogelstein, G. Cauwenberghs, “Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses,” IEEE Transactions on Neural Networks, 2007a.
- R.J. Vogelstein, U. Mallik, E. Culurciello, G. Cauwenberghs, R. Etienne-Cummings, “A multichip neuromorphic system for spike-based visual information processing,” Neural Computation, vol. 19, pp. 2281-2300, 2007b.
- L. Watts, D. Kerns, R. Lyon, and C. Mead, “Improved implementation of the silicon cochlea,” IEEE Journal of Solid-state circuits, vol. 27, no. 5, pp. 692–700, 1992.
- B.Wen and K. Boahen, “A silicon cochlea with active coupling,” IEEE Transactions on Biomedical Circuits and Systems, vol. 3, no. 6, pp. 444–455, 2009.
- K. Zaghloul and K. Boahen, “A silicon retina,” Journal of Neural Engineering, vol. 3, pp. 257–267, 2006.
- Q. Zou, Y. Bornat, J. Tomas, S. Renaud, and A. Destexhe, “Real-time simulations of networks of Hodgkin-Huxley neurons using analog circuits,” Neurocomputing, vol. 69, pp. 1137-1140, 2006.